This invention relates to a method of depositing a thin film used in the fabrication of polysilicon (p-Si) thin-film-transistors (TFT), and more particularly, to a method of producing a semiconductor device utilizing metal induced crystallization while suppressing partial solid phase crystallization.
The demand for smaller electronic consumer products with higher resolution displays spurs continued research and development in the area of liquid crystal displays (LCDs). The primary component of the LCD is the TFT. TFTs typically are fabricated on a transparent substrate such as quartz, glass, or even plastic, and employ a thin film silicon semiconductor.
There are two types of thin film silicon semiconductors; amorphous silicon semiconductors (a-Si) and crystalline silicon conductors, also called polysilicon semiconductors (p-Si). Amorphous silicon semiconductors are most commonly used because they can be fabricated relatively inexpensively through mass production. Polysilicon semiconductors have superior physical properties, such as electrical conductivity, when compared to a-Si semiconductors. Polysilicon semiconductors, however, are more difficult to produce than are a-Si semiconductors. Due to the superior properties of p-Si semiconductors, much research has been focused on improving the process of fabricating p-Si semiconductors.
One method currently under study involves transforming a-Si films to p-Si films by utilizing metal induced crystallization (MIC). The a-Si films used in the processes of the prior art are silicon films deposited by chemical vapor deposition (CVD) techniques, such as plasma enhanced CVD, as known in the art. MIC is a popular method of transforming the chemical vapor deposited a-Si films to p-Si films because the process uses low thermal budgets, i.e., high temperatures and short annealing times, or relatively low temperatures with longer annealing times. This low thermal budget MIC process is important because the glass substrates typically used in LCDs cannot withstand high annealing temperatures and/or long annealing times without deforming or breaking. For example, glass typically breaks or deforms at temperatures of approximately 750xc2x0 C. Other substrates, such as quartz, which can withstand higher temperatures and longer annealing times, typically are cost prohibitive for use in LCD devices. In the MIC process, a higher annealing temperature is generally desired so as to minimize the required annealing time. Due to the constraint of glass substrates, current MIC processes typically are carried out between 650xc2x0 C. and 750xc2x0 C. (the highest temperatures typically allowed without deforming the glass substrate). However, this annealing temperature range constrains the throughput requirements, i.e., the annealing time required, and the conditions of the MIC process. The annealing time and the temperature of the process both effect the material characteristics of the resulting film. Accordingly, a disadvantage of the current MIC process is that the characteristics of the p-Si films created are constrained by the temperature and throughput limitations imposed by the current process.
Another disadvantage of the current MIC process is the problem of partial solid phase crystallization (SPC) in the film. If partial SPC occurs during the MIC process, the material characteristics of the p-Si film will vary significantly across the film. These variations cause significant topological irregularities in the TFT device which hinders its performance. Accordingly, it is desirable to eliminate the SPC growth mode so that MIC will be the only mechanism underlying the silicon phase transformation.
In one method of the prior art MIC process, the metal catalyst is introduced into the film through appropriately positioned windows. These windows typically are positioned surrounding the areas where each TFT is to be fabricated. Accordingly, the metal catalyst is not introduced uniformly in the film, but only at selected areas. Nucleation and crystalline growth commences from these areas first. As the crystalline fronts develop from the sites where the metal catalyst has been introduced, the fronts propagate forward and crystallize sufficiently large regions so as to allow room for fabrication of each TFT device. Outside these regions the silicon material remains in the amorphous phase and is etched, i.e., removed, in subsequent steps.
During propagation of the metal induced crystallization fronts in the film, undesirable random nucleation and growth of silicon, also referred to as SPC, is also possible. Solid phase crystallization can become the dominant crystalline growth mechanism under certain operating conditions. In particular, partial SPC typically occurs at higher crystallization temperatures, i.e., temperatures greater than 700xc2x0 C., and/or at long crystallization times, i.e., greater than 200 seconds. As stated above, these SPC crystallization temperatures and time frames fall squarely within the desired temperature range of the current MIC process. Accordingly, the occurrence of SPC further limits the crystallization temperature range to below 700xc2x0 C., which increases the annealing time and lowers the throughput of the current MIC process.
In addition, in the MIC process it is desirable to maximize the lateral growth length of the crystallized portion of the film. In other words, it is desirable to maximize the extent that the crystalline growth front advances before its stops due the depletion of the catalyst originally deposited in the introduction window. Depletion of the catalyst reduces the amount of catalyst left in the film as an impurity. Because the lateral growth length of the crystallized portion is maximized by long annealing times and/or high annealing temperatures, the issue of suppressing partial SPC during the MIC process becomes even more important at the desired annealing temperatures.
Thus far, the solution has been to restrict the operating window of the MIC process to conditions which minimize partial SPC and at the same time attempt to achieve the desirable lateral growth length of the crystalline growth front, i.e., to a length greater than 50 xcexcm. However, the operating window is quite limiting and interferes with throughput requirements. For example, current MIC processes typically operate at a temperature in a range of 650 to 700xc2x0 C., with an annealing time of 200 seconds. The film that is created retains a relatively large amount of the metal catalyst as an impurity and has spatial irregularities due to formation of the crystalline structure by both MIC and SPC processes. Increasing the annealing time to over 1000 seconds will eliminate much of the catalyst remaining in the film but will increase the amount of SPC which occurs. Moreover, the 1000 second annealing time is a throughput limitation for the process.
Accordingly, it would be advantageous to have a method of creating a p-Si film having uniform characteristics across the film.
It would also be advantageous to have a method of creating a p-Si film which utilizes metal induced crystallization and which suppresses solid phase crystallization.
It would also be advantageous to have a method of forming a p-Si film by MIC utilizing higher temperatures and shorter annealing times than prior art processes.
It would further be advantageous to have a method of creating a p-Si film in which the metal catalyst is substantially depleted.
A MIC process is provided which employs an a-Si film precursor deposited by physical vapor deposition (PVD), wherein the precursor film does not readily undergo crystallization by standard SPC processes. Using this PVD a-Si precursor, the a-Si film is transformed to p-Si by the MIC method wherein the crystalline growth occurs fastest at regions that have been augmented with a metal catalyst and proceeds extremely slowly, practically zero, at regions which bear no metal catalyst. Accordingly, by use of the PVD a-Si precursor in the process of the present invention, the MIC process may take place at higher annealing temperatures and shorter annealing times without SPC taking place. The process has a faster throughput than previous MIC processes, results in a p-Si film having virtually no catalyst impurities remaining in the film, and a film having spatially uniform characteristics.